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wireless components data sheet revision 1.6, 2010-12-21 tda 5201 ask single conversion receiver version 1.6
edition 2010-12-21 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
tda 5201 ask single conversion receiver data sheet 3 revision 1.6, 2010-12-21 trademarks of infineon technologies ag aurix?, bluemoon?, c166?, ca npak?, cipos?, cipurse?, comn eon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobri dge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfe t?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pr o-sil?, profet?, rasic?, re versave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlew is?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x-go ld?, x-pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nx p. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave offi ce? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. open wave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius sate llite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of sy mbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. t ektronix? of tektroni x inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments inco rporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2010-10-26 revision history page or item subjects (major changes since previous revision) previous revision: 1.5 revision 1.6, 2010-12-21 all converted into structured framemaker (edd 3.4) 4-3 more detailed explanation of agc 5-5, 5-7 more detailed information of lna high gain mode and lna low gain mode 5-3, 5-4 enhanced sensitivity values
tda 5201 ask single conversion receiver table of contents data sheet 4 revision 1.6, 2010-12-21 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1product info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 pin definition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.1 low noise amplifier (lna) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.2 mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.3 pll synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.4 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.5 limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.6 data filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.7 data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.8 peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.9 bandgap reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 choice of lna threshold voltage and time constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 data filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 quartz load capacitance calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 quartz frequency calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 data slicer threshold generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.1 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.2 test board layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.3 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 appendix - noise figure and gain circles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table of contents
tda 5201 ask single conversion receiver list of figures data sheet 5 revision 1.6, 2010-12-21 figure 1 pg-tssop-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2 pg-tssop-28 package outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3 ic pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4 main block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5 lna automatic gain control circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6 typical curve of rssi level and permissive agc threshold levels . . . . . . . . . . . . . . . . . . . . . . 22 figure 7 data filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8 determination of series capacita nce value for the quartz oscillator . . . . . . . . . . . . . . . . . . . . . . 24 figure 9 data slicer threshold generation wi th external r-c integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10 data slicer threshold generation utilizing the peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11 schematic of the evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12 top side of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 13 bottom side of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 14 component placement on the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 15 gain and noise circles of the tda5201 at 315 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 list of figures
tda 5201 ask single conversion receiver list of tables data sheet 6 revision 1.6, 2010-12-21 table 1 pin definition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2 csel pin operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3 pdwn pin operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4 pll division ratio dependence on states of csel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5 absolute maximum ratings, ambient temperature t amb = - 40 c ... + 85 c . . . . . . . . . . . . . . . 27 table 6 operating range, ambient temperature t amb = - 40 c ... + 85 c . . . . . . . . . . . . . . . . . . . . . . . 27 table 7 ac/dc characteristics with t amb = 25 c, v cc = 4.5 ... 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9 bill of materials addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 list of tables
tda 5201 ask single conversion receiver product info data sheet 7 revision 1.6, 2010-12-21 1 product info general description the ic is a very low power consumpt ion single chip ask single conversion receiver for receive frequencies between 310 mhz and 350 mhz. the receiver offers a high level of integration and needs only a few external components. the device contains a low noise amplifier (lna ), a double balanced mixer, a fully integrated vco, a pll synthesizer, a crystal osc illator, a limiter with rssi ge nerator, a data filter, a data comparator (slicer) and a peak detector. additionally there is a power down feature to save battery life. features ? low supply current ( i s = 4.6 ma typ.) ? supply voltage range 5 v 10 % ? power down mode with very low supply current (50 na typ) ? fully integrated vco and pll synthesizer ? rf input sensitivity < ? 110 dbm ? selectable frequency ranges around 315 mhz and 345 mhz ? selectable reference frequency ? limiter with rssi generation, operating at 10.7 mhz ?2 nd order low pass data filt er with external capacitors ? data slicer with self-adjusting threshold application ? keyless entry systems ? remote control systems ? fire alarm systems ? low bitrate communication systems package figure 1 pg-tssop-28 ordering information type ordering code package 1) 1) available on tape and reel tda5201 sp000012902 pg-tssop-28
tda 5201 ask single conversion receiver product description data sheet 8 revision 1.6, 2010-12-21 2 product description 2.1 overview the ic is a very low power consum ption single chip ask super heterodyne receiver (s hr) for the frequency bands 315 mhz and 345 mhz. the shr offers a high level of integration and needs only a few external components. the device contains a low noise amplifier (lna ), a double balanced mixer, a fully integrated vco, a pll synthesizer, a crystal osc illator, a limiter with rssi ge nerator, a data filter, a data comparator (slicer) and a peak detector. additionally there is a power down feature to save battery life. 2.2 application ? keyless entry systems ? remote control systems ? fire alarm systems ? low bitrate communication systems 2.3 features ? low supply current ( i s = 4.6 ma typ.) ? supply voltage range 5 v 10 % ? power down mode with very low supply current (50 na typ.) ? fully integrated vco and pll synthesizer ? rf input sensitivity < ? 110 dbm ? selectable receive frequency bands 315 mhz and 345 mhz ? selectable reference frequency ? limiter with rssi generation, operating at 10.7 mhz ?2 nd order low pass data filt er with external capacitors ? data slicer with self-adjusting threshold
tda 5201 ask single conversion receiver product description data sheet 9 revision 1.6, 2010-12-21 2.4 package outlines figure 2 pg-tssop-28 package outlines
tda 5201 ask single conversion receiver functional description data sheet 10 revision 1.6, 2010-12-21 3 functional description 3.1 pin configuration figure 3 ic pin configuration crst2 pdwn pdo data 3vout thres ffb opp sln slp limx lim csel lf crst1 vcc lni tagc agnd lno vcc mi mix agnd fsel ifo dgnd vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 tda 5201
tda 5201 ask single conversion receiver functional description data sheet 11 revision 1.6, 2010-12-21 3.2 pin definition and function table 1 pin definition and function pin no. name pin type buffer type function 1 crst1 in/out external crystal connector 1 2vccin 5 v supply 3lni in lna input 4.15v 50ua 1 57ua 4k 1k 3 500ua
tda 5201 ask single conversion receiver functional description data sheet 12 revision 1.6, 2010-12-21 4tagcin/out agc time constant control 5agndin analogue ground return 6lnoout lna output 7vccin 5 v supply 8mi in mixer input table 1 pin definition and function (cont?d) pin no. name pin type buffer type function 1k 4.2ua 1.5ua 1.7v 4.3v 4 6 1k 5v 8 1.7v 9 400ua 2k 2k
tda 5201 ask single conversion receiver functional description data sheet 13 revision 1.6, 2010-12-21 9 mix in complementary mixer input 10 agnd in analogue ground return 11 fsel not applicable - has to be left open 12 ifo out if mixer output 10.7 mhz 13 dgnd in digital ground return 14 vdd in 5 v supply pll counter circuitry table 1 pin definition and function (cont?d) pin no. name pin type buffer type function 8 1.7v 9 400ua 2k 2k 2.2v 4.5k 60 12 300ua
tda 5201 ask single conversion receiver functional description data sheet 14 revision 1.6, 2010-12-21 15 lf in/out pll filter access point 16 csel in quartz selector 5.xx mhz or 10.xx mhz 17 lim in limiter input table 1 pin definition and function (cont?d) pin no. name pin type buffer type function 15 200 30ua 30ua 4.6v 2.4v 5v 100 1.2v 80k 16 330 15k 15k 18 17 2.4v 75ua
tda 5201 ask single conversion receiver functional description data sheet 15 revision 1.6, 2010-12-21 18 limx in complementary limiter input 19 slp in data slicer positive input 20 sln in data slicer negative input 21 opp in opamp noninverting input table 1 pin definition and function (cont?d) pin no. name pin type buffer type function 330 15k 15k 18 17 2.4v 75ua 9 40ua 15ua 3k 100 5ua 20 10k 21 200 5ua
tda 5201 ask single conversion receiver functional description data sheet 16 revision 1.6, 2010-12-21 22 ffb in data filter feedback pin 23 thres in agc threshold input 24 3vout out 3 v reference output 25 data out data output 26 pdo out peak detector output table 1 pin definition and function (cont?d) pin no. name pin type buffer type function 100k 5ua 22 10k 5ua 23 3v 24 25 200 80k 26 200
tda 5201 ask single conversion receiver functional description data sheet 17 revision 1.6, 2010-12-21 27 pdwn in power down input 28 crst2 in/out external crystal connector 2 table 1 pin definition and function (cont?d) pin no. name pin type buffer type function 27 220k 220k 4.15v 50ua 28
tda 5201 ask single conversion receiver functional description data sheet 18 revision 1.6, 2010-12-21 3.3 functional block diagram figure 4 main block diagram if filter vdd v cc lno mi mix ifo lim limx ffb opp slp sln data pdo slicer rssi thres lna rf tagc dgnd vcc agnd fsel csel pdwn crystal loop filter bandgap reference u ref tda 5201 agc reference 3vout 3 4 14 13 2/7 5/10 11 15 lf 16 1 28 27 24 23 26 25 20 19 21 22 18 17 12 9 8 6 crystal osc det : 128/64 vco : 1/2
tda 5201 ask single conversion receiver functional description data sheet 19 revision 1.6, 2010-12-21 3.4 functional blocks 3.4.1 low noise amplifier (lna) the lna is an on-chip cascode amplifier with a voltage gain of 15 db to 20 db. the gain figure is determined by the external matching netw orks situated ahead of ln a and between the lna output lno (pin 6) and the mixer inputs mi and mix (pin 8 and pin 9). the noise figure of the lna is approximately 2 db, the current consumption is 500 a. the gain can be reduced by approximately 18 db. the switching point of this agc action can be determined externally by applying a threshold voltage at the thres pin (pin 23). this voltage is compared internally with the received signal (r ssi) level generated by the limiter circui try. in case that the rssi level is higher than the threshold voltage the lna gain is reduc ed and vice versa. the threshold voltage can be generated by attaching a voltage divider between the 3vout pin (pin 24) which provides a temperature stable 3 v output generated from the internal bandgap voltage and the thres pin as described in chapter 4.1 . the time constant of the agc action can be determined by connecting a capacitor to the tagc pin (pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operating case and interference scenario to be expected during operation. the optimum choice of agc time constant and the threshold voltage is described in chapter 4.1 . 3.4.2 mixer the double balanced mixer down-converts the input frequen cy (rf) in the range of 310 mhz to 350 mhz to the intermediate frequency (if) at 10.7 mhz with a voltage gain of approximately 21 db by utilizing either high- or low- side injection of the loca l oscillator signal. in case the mixer is interfaced only sing le-ended, the unused mixer input has to be tied to ground via a capacitor. the mixer is foll owed by a low pass filter with a corner frequency of 20 mhz in order to suppress rf signals to appear at the if output ( ifo pin). the if output is internally consisting of an emitter follower that has a source impedance of approximately 330 ? to facilitate interfacin g the pin directly to a standard 10.7 mhz ceramic filter without additional matching circuitry. 3.4.3 pll synthesizer the phase locked loop synthesizer consists of a vco, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. the vco is including spiral inductors and varactor diodes. the fsel pin (pin 11) has to be left open. the tuning range of the vco was designed to guarantee over production spread and the specified temperature ra nge a receive frequency range between 310 mhz and 350 mhz depending on whether high- or lo w-side injection of the local oscilla tor is used. the oscillator signal is fed both to the synthesizer divider chai n and to a divider that is dividing the signal by 2 before it is applied to the down-converting mixer. local oscillator high side inje ction has to be used for receive frequencies between approximately 310 mhz and 330 mhz, low side injection for receive frequencies between 330 mhz and 350 mhz - see also chapter 4.4 . 3.4.4 crystal oscillator the on-chip crystal oscillator circuitry allows for utilization of quartzes both in the 5 mhz and 10 mhz range as the overall division ratio of the pll can be switched between 64 and 128 via the csel (pin 16) pin according to the following table. table 2 csel pin operating states csel crystal frequency open 5.xx mhz shorted to ground 10.xx mhz
tda 5201 ask single conversion receiver functional description data sheet 20 revision 1.6, 2010-12-21 the calculation of the value of the necess ary quartz load capacitance is shown in chapter 4.3 , the quartz frequency calculation is explained in chapter 4.4 . 3.4.5 limiter the limiter is an ac coupled multis tage amplifier with a cumulative gain of approximately 80 db that has a bandpass-characteristic centered around 10.7 mhz. it has an input impedance of 330 ? to allow for easy interfacing to a 10.7 mhz ceramic if filter. the limiter ci rcuit acts as a receive signal strength indicator (rssi) generator, which produces a dc voltage that is directly pr oportional to the input signal level as can be seen in figure 6 . this signal is used to demodulate the ask receiv e signal in the subsequent baseband circuitry and to turn down the lna gain by approximately 18 db in case the input signal strength is too strong as described in chapter 3.4.1 and chapter 4.1 . 3.4.6 data filter the data filter comprises an op-amp with a bandwidth of 100 khz used as a voltage follower and two 100 k ? on- chip resistors. along with two external capacitors a 2 nd order sallen-key low pass filter is formed. the selection of the capacitor values is described in chapter 4.2 . 3.4.7 data slicer the data slicer is a fast comparator with a bandwidth of 100 khz. this allows for a maximum receive data rate of approximately 120 kbaud. the maximum achievable data rate also depends on the if filter bandwidth and the local oscillator tolerance val ues. both inputs are accessible. the output delivers a digital data signal (cmos-like levels) for the detector. the self-adjusting thresh old on pin 20 is generated by rc-term or peak detector depending on the baseband coding schem e. the data slicer threshold genera tion alternatives are described in more detail in chapter 4.5 . 3.4.8 peak detector the peak detector generates a dc voltage which is proporti onal to the peak value of the receive data signal. an external rc network is necessary. the output can be used as an indicator for the sig nal strength and also as a reference for the data slicer. the maximum output current is 500 a. 3.4.9 bandgap reference circuitry a bandgap reference circuit provides a temperature stab le reference voltage for the device. a power down mode is available to switch off all sub-circuits which is co ntrolled by the pwdn pin (pin 27) as shown in the following table. the supply current drawn in this case is typically 50 na. table 3 pdwn pin operating states pdwn operating state open or tied to ground power down mode tied to v cc receiver on
tda 5201 ask single conversion receiver applications data sheet 21 revision 1.6, 2010-12-21 4 applications 4.1 choice of lna threshold voltage and time constant in the following figure the internal circuitry of the lna automatic gain control is shown. figure 5 lna automatic gain control circuitry the lna automatic gain control circui try consists of an operational transi mpedance amplifier that is used to compare the received signal strength signal (rssi) generat ed by the limiter with an externally provided threshold voltage u thres . as shown in the following figure the threshold voltage can have any value between approximately typically 0.8 v and 2.8 v to provide a switching point within the receive signal dynamic range. this voltage u thres is applied to the thres pin (pin 23). the threshold voltage can be generated by attaching a voltage divider between the 3vout pin (pin 24) which provides a temper ature stable 3 v output generated from the internal bandgap voltage and the thres pin. if the rssi level generated by the limiter is higher than u thres , the ota generates a positive current i load . this yields a voltage rise on the tagc pin (pin 4). otherwise, the ota generates a negative current. these currents do not have the same values in order to achieve a fast-attack and slow-release action of the agc and are used to charge an external capacitor which finally generates the lna gain control voltage. pins: 24 23 4 lna r4 r5 u threshold rssi (0.8 - 2.8v) v cc gain control voltage ota +3v i load rssi > u threshold : i load =4.2a rssi < u threshold : i load = -1.5a u c c u c :< 2.6v : gain high u c :> 2.6v : gain low u cmax = v cc -0.7v u cmin = 1.67v
tda 5201 ask single conversion receiver applications data sheet 22 revision 1.6, 2010-12-21 figure 6 typical curve of rssi level and permissive agc threshold levels the switching point should be chosen according to th e intended operating scenario. the determination of the optimum point is described in the accompanying applicatio n note, a threshold voltage level of 1.8 v is apparently a viable choice. it should be noted that the output of the 3vout pin is capable of drivin g up to 50 a, but that the thres pin input current is only in the region of 40 na. as the current drawn out of the 3vout pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. r4 can be chosen as 120 k ? , r5 as 180 k ? to yield an overall 3vout output current of 10 a. notes 1. to keep the lna in high gain mode for the complete rf-input level range a voltage equal or higher than 3.3 v has to be applied at pin 23. alternativ ely, pin 23 has to be connected to pin 24 and pin 4 has to be connected to gnd. in addition this would save an external capacitor. 2. to keep the lna in low gain mode for the complete rf-input level range a voltage lower than 0.7 v has to be applied to the thres pin (e.g. thres connected to gn d). in the above-mentioned mode pin 4 has to be connected by a c apacitor to gnd. 3. as stated above, the gain control vo ltage of the lna is gener ated at the capacitor connected to the tagc pin by the charging and discharging curren ts of the ota. consequently this ca pacitor is responsible for the agc time constant. as the charging and discharging currents are not equal two different ti me constants will result. the time constant corresponding to the charging process of the capacito r shall be chosen according to the data rate. according to measurements performed at infi neon the capacitor value should be greater than 47 nf. lna always in high gain mode 0 0.5 1 1.5 2 2.5 3 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 input level at lna input [dbm] u thres voltage range rssi level range lna always in low gain mode rssi level
tda 5201 ask single conversion receiver applications data sheet 23 revision 1.6, 2010-12-21 4.2 data filter design utilizing the on-board voltag e follower and the two 100 k ? on-chip resistors a 2 nd order sallen-key low pass data filter can be constructed by adding 2 external capac itors between pin 19 (slp) and pin 22 (ffb) and to pin 21 (opp) as depicted in the following figure and described in the following formulas 1) . figure 7 data filter design (1) (2) with (3) 1) taken from tietze/schenk: halbleit erschaltungstechnik, springer berlin, 1999 the quality factor of the poles where in case of a bessel filter a = 1.3617, b = 0.618 and thus q = 0.577 and in case of a butterworth filter a = 1.141, b = 1 and thus q = 0.71 example butterworth filter with f 3db = 5 khz and r = 100 k ? c 1 = 450 pf, c 2 = 225 pf pins: 22 21 19 rr 100k 100k c 1 c 2 db f r b q c 3 2 2 1 = db f qr b c 3 4 2 = a b q =
tda 5201 ask single conversion receiver applications data sheet 24 revision 1.6, 2010-12-21 4.3 quartz load capacitance calculation the value of the capacitor nece ssary to achieve that the quartz oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in chapter 1.1.3 and by the quartz specifications gi ven by the quartz manufacturer. figure 8 determination of series capacitance value for the quartz oscillator crystal specified with load capacitance (4) with c l the load capacitance (refer to the quartz crystal specification). these values may be obtained by putting two capacitors in series to the quartz, such as 18 pf and 22 pf in the 5.1 mhz case and 18 pf and 12 pf in the 10.2 mhz case. but please note that the calculated value of c s includes the parasitic capacitors also. examples 5.1 mhz c l = 12 pf x l = 580 ? c s = 9.8 pf 10.18 mhz c l = 12 pf x l = 870 ? c s = 7.2 pf c s crystal input impedance z 1-28 tda5201 pin 28 pin 1 l l s x f c c 2 1 1 + =
tda 5201 ask single conversion receiver applications data sheet 25 revision 1.6, 2010-12-21 4.4 quartz frequency calculation as described in chapter 3.4.3 , the operating range of the on-chip vco is wide enough to guarantee a receive frequency range between 310 mhz and 350 mhz. the vco sign al is divided by 2 before applied to the mixer . this local oscillator signal can be us ed to down-convert the rf signals both with high- or low-side injection at the mixer. high-side injection of the lo cal oscillator has to be used for rece ive frequencies betw een 310 mhz and 330 mhz. in this case the local oscillato r frequency is calculated by adding the if frequency (10.7 mhz) to the rf frequency. low-side injection has to be used fo r receive frequencies between 330 mhz and 350 mhz. the local oscillator frequency is calculated by subtracting the if frequen cy (10.7 mhz) from the rf frequency then. the overall division ratios in the pll are 64 or 32 depending on w hether the csel-pin is left open or tied to ground. therefore, the quartz frequency may be calculated by using the following formula: (5) with example addition of 10.7 is used in case of operation the device at 315 mhz, subtract ion in case of operation at 345 mhz for instance. this yields the following frequencies: csel tied to gnd: (6) (7) csel open: (8) (9) ? rf receive frequency ? lo local oscillator (p ll) frequency ( ? rf 10.7) ? qu quartz oscillator frequency r ratio of local oscillator (pll) fr equency and qu artz frequency as shown in the subsequent table table 4 pll division ratio dependence on states of csel csel ratio r = ( ? lo / ? qu ) open 64 gnd 32 r f f rf qu 7 . 10 ? = () mhz mhz mhz f 1781 . 10 32 / 7 . 10 315 qu mhz mhz mhz f 4469 . 10 32 / 7 . 10 345 qu mhz mhz mhz f 0891 . 5 64 / 7 . 10 315 qu mhz mhz mhz f 2234 . 5 64 / 7 . 10 345 qu
tda 5201 ask single conversion receiver applications data sheet 26 revision 1.6, 2010-12-21 4.5 data slicer threshold generation the threshold of the data slicer especially for a coding scheme without dc-content, can be generated in two ways, depending on the signal coding scheme used. in case of a signal coding scheme without dc content such as manchester coding the threshold can be generated using an external rc-integrator as shown in figure 9 . the time constant t a of the rc-integrator has to be significantly lar ger than the longest period of no signal change t l within the data sequence. in order to keep distortion low, the minimum value for r is 20 k ? . figure 9 data slicer threshold generation with external r-c integrator another possibility for threshol d generation is to use the peak detector in connecti on with two resistors and one capacitor as shown in the following figure. the component values are dep ending on the coding scheme and the protocol used. figure 10 data slicer threshold generation utilizing the peak detector pins: 20 19 r c 25 data out u threshold data slicer data filter pins: 20 19 25 data out u threshold data slicer data filter 26 peak detector c r r
tda 5201 ask single conversion receiver electrical characteristics data sheet 27 revision 1.6, 2010-12-21 5 electrical characteristics 5.1 electrical data 5.1.1 absolute maximum ratings attention: the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic will result. 5.1.2 operating range within the operating range the ic opera tes as explained in the circuit description. the ac/dc characteristic limits are not guaranteed. supply voltage: v cc = 4.5 v ... 5.5 v table 5 absolute maximum ratings, ambient temperature t amb = - 40 c ... + 85 c parameter symbol values unit note / test condition number min. typ. max. supply voltage v s -0.3 5.5 v 1.1 junction temperature t j -40 +125 c 1.2 storage temperature t s -40 +150 c 1.3 thermal resistance r thja 114 k/w 1.4 esd hbm integrity, all pins v esd 1,5 kv aec q100-002 / jesd22-a114b 1.5 esd sdm integrity, all pins v esd 750 v ainsi / esd sp5.3.2-2008 1.6 table 6 operating range, ambient temperature t amb = - 40 c ... + 85 c parameter symbol values unit note / test condition test number min. typ. max. supply current i s 5.2 ma f rf = 315 mhz 2.1 receiver input level rf in -111 -13 dbm @ source impedance 50 ? , ber 2e-3, average power level, manchester encoded data rate 4 kbit, 280 khz if bandwidth 2.2 lni input frequency f rf 310 350 mhz 2.3 mi/x input frequency f mi 310 350 mhz 2.4 3 db if frequency range f if -3 db 523mhz 2.5
tda 5201 ask single conversion receiver electrical characteristics data sheet 28 revision 1.6, 2010-12-21 attention: test means that the parameter is not subject to production test. it was verified by design/characterization. 5.1.3 ac/dc characteristics ac/dc characteristics involve the sp read of values guaranteed within the specified voltage and ambient temperature range. typical characteristics are the median of the production. power mode off v off 00.8v 2.6 power mode off v on 2 v cc v2.7 gain control voltage, lna high gain state v thres 2.8 v cc -1 v 2.8 gain control voltage, lna low gain state v thres 00.7v 2.9 table 7 ac/dc characteristics with t amb = 25 c, v cc = 4.5 ... 5.5 v parameter symbol values unit note / test condition test number min. typ. max. supply current supply current standby mode i s pdwn 50 70 na pin 27 (pdwn) open or tied to 0 v 3.1 supply current i s 4.6 5 ma 3.2 lna - signal input lni (pin 3), v thres > 3.3 v, high gain mode average power level at ber = 2e-3 (sensitivity) rf in -113 dbm manchester encoded data rate 4 kbit, 280 khz if bandwidth 3.3 input impedance f rf = 315 mhz s 11 lna 0.895 / -25.5 deg 3.4 input level @ 1 db c.p. f rf =315mhz p1db lna -14 dbm 3.5 input 3rd order intercept point f rf = 315 mhz iip3 lna -10 dbm f in = 315 mhz & 317 mhz 3.6 lo signal feedthrough at antenna port lo lni -119 dbm 3.7 lna - signal output lno (pin 6), v thres > 3.3 v, high gain mode gain f rf = 315 mhz s 21 lna 1.577 / 150.3 deg 3.8 output impedance, f rf =315mhz s 22 lna 0.897 / -10.3 deg 3.9 voltage gain antenna to mi f rf =315mhz g antmi 21 db 3.10 table 6 operating range, ambient temperature t amb = - 40 c ... + 85 c (cont?d) parameter symbol values unit note / test condition test number min. typ. max.
tda 5201 ask single conversion receiver electrical characteristics data sheet 29 revision 1.6, 2010-12-21 noise figure nf lna 2dbexcluding matching network loss see appendix 3.11 lna - signal input lni, v thres = gnd, low gain mode input impedance f rf =315mhz s 11 lna 0.918 / -25.2 deg 3.12 input level @ 1 db c. p. f rf =315mhz p1db lna -7 dbm matched input 3.13 input 3 rd order intercept point f rf =315mhz iip3 lna -13 dbm f in = 315 mhz and 317 mhz 3.14 lna - signal output lno, v thres = gnd, low gain mode gain f rf =315mhz s 21 lna 0.007 / 153.7 deg 3.15 output impedance , f rf =315mhz s 22 lna 0.907 / -10.5 deg 3.16 voltage gain antenna to mi f rf =315mhz g antmi 2db 3.17 agc - signal 3vout (pin 24) output voltage v 3vout 3v 3.18 current out i 3vout 50 a 3.19 agc - signal thres (pin 23) input voltage range v thres 0 v cc -1 v see chapter 4.1 3.20 lna low gain mode v thres 0v 3.21 lna high gain mode v thres 3.3 1) v cc -1 1) v voltage must not be higher than v cc -1 v 3.22 current in i thres_in 5na 3.23 agc - signal tagc (pin 4) current out, lna low gain state i tagc_out 4.2 a rssi > v thres 3.24 current in, lna high gain state i tagc_in 1.5 a rssi < v thres 3.25 mixer - signal input mi/mix (pins 8/9) input impedance f rf =315mhz s 11 mix 0.954 / -10.9 deg 3.26 input 3 rd order intercept point iip3 mix -25 dbm 3.27 mixer - signal output ifo (pin 12) output impedance z ifo 330 ? 3.28 table 7 ac/dc characteristics with t amb = 25 c, v cc = 4.5 ... 5.5 v (cont?d) parameter symbol values unit note / test condition test number min. typ. max.
tda 5201 ask single conversion receiver electrical characteristics data sheet 30 revision 1.6, 2010-12-21 conversion voltage gain f rf =315mhz g mix +21 db 3.29 noise figure, ssb (~dsb nf + 3 db) nf mix 13 db 3.30 rf to if isolation a rf-if 46 db 3.31 limiter - signal input lim/limx (pins 17/18) input impedance z lim 264 330 396 ? 3.32 rssi dynamic range dr rssi 60 80 db 3.33 rssi linearity lin rssi 1 db 3.34 operating frequency (3 db points) f lim 510.723mhz 3.35 data filter useable bandwidth bw bb filt 100 khz 3.36 rssi level at data filter output slp rssi low 1.1 v lna in high gain rf in = -103 dbm 3.37 rssi level at data filter output slp rssi high 2.65 v lna in high gain rf in = -30 dbm 3.38 slicer - signal output data (pin 25) useable bandwidth bw bb slic 100 khz 3.39 capacitive loading of output c max slic 20 pf 3.40 low output voltage v slic_l 0v 3.41 high output voltage v slic_h v cc -1.3 v cc -1 v cc -0.7 v output current =200a 3.42 output current i slic_out 200 a 3.43 peak detector - signal output pdo (pin 26) low output voltage v slic_l 0v 3.44 high output voltage v slic_h v cc -1 v 3.45 load current i load -500 a static load current must not exceed -500 a 3.46 leakage current i leakage 700 na 3.47 crystal oscillator - signals crst1, crst2, (pins 1/28) operating frequency f crstl 5 11 mhz fundamental mode, series resonance 3.48 input impedance @~5mhz z 1-28 -760 + j580 ? 3.49 input impedance @~10mhz z 1-28 -600 + j870 ? 3.50 table 7 ac/dc characteristics with t amb = 25 c, v cc = 4.5 ... 5.5 v (cont?d) parameter symbol values unit note / test condition test number min. typ. max.
tda 5201 ask single conversion receiver electrical characteristics data sheet 31 revision 1.6, 2010-12-21 attention: test means that the parameter is not subject to production test. it was verified by design/characterization. serial capacity @~5mhz c s5 = c1 9.3 pf 3.51 serial capacity @~10mhz c s10 = c1 6.4 pf 3.52 pll - signal lf (pin 15) tuning voltage relative to v cc v tune 0.4 1.6 2.4 v 3.53 power down mode - signal pdwn (pin 27) power mode on v on 2.8 v cc v3.54 power mode off v off 0 0.8 v 3.55 input bias current pdwn i pdwn 19 a 3.56 start-up time until valid if signal is detected t su 1 ms depends on the used crystal 3.57 pll divider - signal csel (pin 16) f crstl range 5.xx mhz v csel 1.4 4 2) v or open 3.58 f crstl range 10.xx mhz v csel 0 0.2 v 3.59 input bias current csel i csel 5 a csel tied to gnd 3.60 1) see chapter 4.1 , choice of lna threshold voltage and time constant 2) maximum voltage in power-on state is 4 v, but in pdwn-state the maximum voltage is 2.8 v. table 7 ac/dc characteristics with t amb = 25 c, v cc = 4.5 ... 5.5 v (cont?d) parameter symbol values unit note / test condition test number min. typ. max.
tda 5201 ask single conversion receiver electrical characteristics data sheet 32 revision 1.6, 2010-12-21 5.2 test board 5.2.1 test circuit the device performance parameters marked with in chapter 5.1.3 are not subject to production test. they were verified by design/characterization. figure 11 schematic of the evaluation board
tda 5201 ask single conversion receiver electrical characteristics data sheet 33 revision 1.6, 2010-12-21 5.2.2 test board layouts figure 12 top side of the evaluation board figure 13 bottom side of the evaluation board
tda 5201 ask single conversion receiver electrical characteristics data sheet 34 revision 1.6, 2010-12-21 figure 14 component placement on the evaluation board
tda 5201 ask single conversion receiver electrical characteristics data sheet 35 revision 1.6, 2010-12-21 5.2.3 bill of materials the following components are necessary for evaluation of the tda5201 at 315 mhz without use of a microchip hcs515 decoder. the following components are necessary in addition to the above mentioned ones for evaluation of the tda5201 in conjunction with a microchip hcs515 decoder. table 8 bill of materials ref value specification r1 100 k ? 0805, 5 % r2 100 k ? 0805, 5 % r3 820 k ? 0805, 5 % r4 120 k ? 0805, 5 % r5 180 k ? 0805, 5 % r6 10 k ? 0805, 5 % l1 15 nh toko, ptl2012-f15n0g l2 12 pf 0805,cog, 2 % c1 3.3 pf 0805, cog, 0.1 pf c2 10 pf 0805, cog, 0.1 pf c3 6.8 pf 0805, cog, 0.1 pf c4 100 pf 0805, cog, 5 % c5 47 nf 1206, x7r, 10 % c6 15 nh toko, ptl2012-f15n0g c7 100 pf 0805, cog, 5 % c8 33 pf 0805, cog, 5 % c9 100 pf 0805, cog, 5 % c10 10 nf 0805, x7r, 10 % c11 10 nf 0805, x7r, 10 % c12 220 pf 0805, cog, 5 % c13 47 nf 0805, x7r, 10 % c14 470 pf 0805, cog, 5 % c15 47 nf 0805, x7r, 10 % c16 18 pf 0805, cog, 0.1 pf c17 12 pf 0805, cog, 2 % q2 (315 + 10.7 mhz)/32 hc49/u, fundamental mode, c l = 12 pf, 315 mhz: jauch q 10.17813-s11-1323-12-10/20 f1 sfe10.7ma5-a murata x2, x3 142-0701-801 johnson x1, x4, s1, s5 2-pole pin connector s4 3-pole pin connector, or not equipped ic1 tda5201 infineon
tda 5201 ask single conversion receiver electrical characteristics data sheet 36 revision 1.6, 2010-12-21 table 9 bill of materials addendum ref value specification r21 22 k ? 0805, 5 % r22 100 k ? 0805, 5 % r23 22 k ? 0805, 5 % r24 820 k ? 0805, 5 % r25 560 k ? 0805, 5 % c21 100 nf 1206, x7r, 10 % c22 100 nf 1206, x7r, 10 % ic2 hcs515 microchip t1 bc 847b infineon d1 ls t670-jl infineon
tda 5201 ask single conversion receiver appendix - noise figure and gain circles data sheet 37 revision 1.6, 2010-12-21 appendix - noise figu re and gain circles the following gain and noise figure circles were measured utilizing micr olab stub stretche rs and a hp8514 network analyzer. maximum gain is shown at point 1 at 18.5 db, minimum noise figure is 1.9 db at point 2, step size of circles is 0.5 db. figure 15 gain and noise circles of the tda5201 at 315 mhz
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